The present invention generally relates to tailoring transistor gate electrode crystal morphology for the formation of integrated circuits. More particularly, the invention relates to processes and structures for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories (EEPROMs).
Memory devices such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), or flash erasable programmable read-only memories (FEPROMs) are erasable and reusable memory cells which are used in digital cellular phones, digital cameras, LAN switches, cards for notebook computers, etc. A memory cell operates by storing electric charge (representing an xe2x80x9conxe2x80x9d state) on an electrically isolated floating gate, which is incorporated into a transistor. This stored charge affects the behavior of the transistor, thereby providing a way to read the memory element. The switching speed of such a memory cell for converting from an xe2x80x9conxe2x80x9d state to an xe2x80x9coffxe2x80x9d state is limited in part by the speed of charge dissipation from the floating gate (i.e., the erase speed). Because faster erase speeds equate to faster switching speeds, efforts have been made to increase the erase speeds of such memory devices, as well as to improve the erase uniformity among the memory cells.
A flash memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically composed of polycrystalline silicon (i.e., xe2x80x9cpolysiliconxe2x80x9d), is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of silicon oxide. Because charge is transferred across the dielectric layer by quantum-mechanical tunneling, this dielectric layer is often referred to as a xe2x80x9ctunnel oxidexe2x80x9d layer. Such tunnel oxide layers are typically approximately 100 xc3x85 thick. Properties of the tunnel oxide must be strictly controlled to ensure the ability to read and write by tunneling, while avoiding data loss through charge trapping or leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as oxide-nitride-oxide (ONO). Electrical access to the floating gate is therefore only through capacitors.
Storing charge on the floating gate programs a memory cell. This is achieved via hot-electron injection by applying a high positive voltage (approximately 12 V) to the control gate, and a high drain-to-source bias voltage (approximately 6 V). An inversion region is created between the source and drain by the control gate voltage, and electrons are accelerated from the source to the drain by the drain bias voltage. Some fraction of these electrons will have sufficient energy to surmount the tunnel oxide barrier height and reach the floating gate. The floating gate is therefore programmed by collecting and storing these electrons to represent an xe2x80x9conxe2x80x9d state.
An EPROM device can be erased (i.e., returned to an xe2x80x9coffxe2x80x9d state) by exposing the floating gate to ultraviolet light, which excites the stored electrons out of the floating gate. The erasure of an EEPROM or FEPROM cell is accomplished via Fowler-Nordheim tunneling, in which applying an electric field, which is sufficient for the stored electrons to traverse the tunnel oxide and enter the substrate, reduces the stored charge in the floating gate. Under this mechanism for discharging the floating gate, a large negative voltage (e.g., xe2x88x9210 V) is applied to the control gate, and a positive voltage (e.g., 5-6 V) is applied to the source while the drain is left floating. Electrons then tunnel from the floating gate through the tunnel oxide, and are accelerated into the source. Because both the programming and erasing of a memory element takes place via charge transfer processes across the tunnel oxide layer, it is important to minimize the defect density in this region that would otherwise create a mechanism for charge trapping or leakage through the tunnel oxide.
A variety of efforts have been aimed at improving the quality of the tunnel oxide and the floating gate for reliable and uniform write and erase characteristics. As critical dimensions continue to shrink, however, maintaining reliability and uniformity while increasing operating speed becomes ever more challenging.
Accordingly, a need exists for improved flash memory device structures and methods of fabrication.
In accordance with one aspect of the present invention, a method of tailoring the crystal morphology of a polysilicon floating gate layer in a flash memory device is provided. The method includes forming a tunnel dielectric layer, and forming nucleation sites on top of the tunnel dielectric layer under a first set of conditions comprising a first temperature and a first atmosphere. A polysilicon layer is formed on top of the nucleation sites under a second set of conditions different from the first set of conditions, the second set of conditions comprising a second temperature and a second atmosphere.
In accordance with another aspect of the invention, a method of tailoring the erase speed and erase uniformity of a flash memory device is provided. The method includes forming a tunnel dielectric layer and forming a polysilicon floating gate layer on the tunnel dielectric layer. The polysilicon floating gate layer has tailored polysilicon grain sizes.
In accordance with yet another aspect of the present invention, a method of tailoring the crystal morphology of a crystalline transistor electrode in an integrated circuit is provided. The method includes forming a dielectric layer, and forming nucleation sites on top of the dielectric layer by exposing the dielectric layer to a first set of deposition conditions selected to optimize grain density. A polycrystalline layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of deposition conditions selected to optimize grain size.
In accordance with yet another aspect of the present invention, a polysilicon floating gate layer in a flash memory device is provided. The polysilicon floating gate layer is formed by forming a tunnel dielectric layer, and forming nucleation sites on top of the tunnel dielectric layer under a first set of conditions comprising a first temperature and a first atmosphere. A polysilicon layer is formed on top of the nucleation sites under a second set of conditions different from the first set of conditions, the second set of conditions comprising a second temperature and a second atmosphere.
In the illustrated embodiments, the crystal morphology of a polysilicon floating gate layer in a flash memory cell is tailored for faster erase speed and more uniform erase characteristics. Advantageously, by separating the nucleation and growth of the polysilicon floating gate layer, the crystal structure and distribution density of the nucleation sites can be selected independently of the polysilicon crystal growth. In this way, the distribution density and grain size of the polysilicon layer can be optimized to produce polysilicon floating gate layers with faster erase speeds and more uniform erase characteristics.